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ace25c 4 00 4 mb serial flash memory ver 1. 2 1 description the ACE25C400 is a 4m - bit ( 512 k - byte) serial flash memory, with advanced write protection mechanisms. the ACE25C400 supports the standard serial peripheral interface (spi), and a high performance dual output as well as dual i/o. the ACE25C400 can be programmed 1 to 512 bytes at a time, using the page program instruction. it is designed to allow either single sector/block at a time or full chip erase operation. the ace25 c 4 00 can be configured to protect part of the memory as the software protect ed mode. the device can sustain a minimum of 100k program/erase cycles on each sector or block. features ? 4m bit of flash memory - 128 uniform sectors with 4k - byte each - 8 uniform block with 64k - byte each - 256 bytes per programmable page ? wide operation range - 2. 7v~3.6v single voltage supply - industrial temperature range ? serial interface - standard spi: clk, cs#, di, do, wp# - dual spi: clk, cs#, dq 0 , dq 1 , wp# - continuous read mode support ? high performance - max fast_read clock frequency: 100mhz - max read clock frequency: 66mhz - typical page program time: 1.5ms - typical sector erase time: 90ms - typical block erase time: 500ms - typical chip erase time: 3.5 s ? low power consumption - typical standby curr ent: 1a ? security - software and hardware write protection - lockable 256 - byte otp se curity sectors - low voltage write inhibit ? high reliability - endurance: 100,000program/erase cycles - data retention: 20years
ace25c 4 00 4 mb serial flash memory ver 1.2 2 packaging type sop - 8 tdfn pin configurations note: 1. dq0 and dq1 are used for dual sip instructions. pin no pin number i/o function 1 cs# i chip select i nput 2 do(dq 1 ) i/o data output (data input output 1) (1) 3 wp# i write protect input 4 gnd ground 5 di(dq 0 ) i/o data input (data input output 0) (1) 6 clk i serial clock input 7 hold# i hold input 8 vcc power supply
ace25c 4 00 4 mb serial flash memory ver 1.2 3 block diagram figure 1 ACE25C400 serial flash memory block diagram ordering information ACE25C400 xx + x h pb - free u : tube t : tape and reel fm: sop - 8 dm : tdfn - 8 halogen - free
ace25c 4 00 4 mb serial flash memory ver 1.2 4 pin descriptions serial clock (clk): the spi seri al clock input (clk) pin provides the timing for serial input and output operations. serial data input, output and i/os (di, do and dq 0 , dq 1 ): the ACE25C400 supports standard spi and dual spi operation. standard spi instructions use the unidirectional d i (input) pin to serially write instructions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge of clk. dual spi instructions use the bidirectional dq pins to serially write instructions, addresses or data to the device on the rising edge of clk and read data or status from the device on the falling edge of clk. chip select (cs#): the spi chip select (c s#) pin enables and disables device operation. when cs# is high, the device is deselected and the serial data output (do, or dq 0 , dq 1 ) pins are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal e rase, program or write status register cycle is in progress. when cs# is brought low, the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, cs# must t ransition from high to low before a new instruction will be accepted. the cs# input must track the vcc supply level at power - up (see 9 write protection and figure 23). if needed a pull - up resister on cs# can be used to accomplish this. hold (hold#): the hold# pin allows the device to be paused while it is actively selected. when hold# is brought low, while cs# is low, the do pin will be at high impedance and signals on the di and clk pins will be ignored (dont care). when hold# is brought high, device o peration can resume. the hold# function can be useful when multiple devices are sharing the same spi signals. the hold# pin is active low. write protect (wp#): the write protect (wp#) pin can be used to prevent the status registers from being written. used in conjunction with the status registers block protect (bp2, bp1 and bp0) bits and status register protect (srp) bits, a portion as small as a 4kb sector or the entire memory array can be hardware protected. the wp# pin is active low.
ace25c 4 00 4 mb serial flash memory ver 1.2 5 memo ry organization the ACE25C400 array is organized into 2 ,0 48 programmable pages of 256 - bytes each. up to 256 bytes can be programmed (bits are programmed from 1 to 0) at a time. pages can be erased in groups of 16 (4kb sector erase), groups of 256 (64kb blo ck erase) or the entire chip (chip erase). the ACE25C400 has 128 erasable sectors and 8 erasable 64 - k byte blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. block (64kb) sector (4kb) address range 7 127 0 7 f000h 0 7 ffffh
ace25c 4 00 4 mb serial flash memory ver 1.2 6 device operations standard spi th e ACE25C400 is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (cs#), serial data input (di) and serial data output (do). standard spi instructions use the di input pin to serially write instructions, addr esses or data to the device on the rising edge of clk. the do output pin is used to read data or status from the device on the falling edge of clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0, the clk signal is normally low on the falling and rising edges of cs#. for mode 3, the clk signal is norma lly high on the falling and rising edges of cs#. figure 2 the difference between mode 0 and mode 3 dual spi the ACE25C400 supports dual spi operation when using instructions such as fast read dual output (3bh) and fast read dual i/o (bbh). the se instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi read instructions are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for executing non - speed - critical code directly from the spi bus (xip). when using dual spi instructions, the di and do pins become bidirectional i/o pins: dq 0 and dq 1 . hold for standard spi and dual spi operations, the hold# signal allows the ACE25C400 operation to b e paused while it is actively selected (when cs# is low). the hold# function may be useful in cases where the spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority inte rrupt requires use of the spi bus. in this case the hold# function can save the state of the instruction and the data in the buffer so programming can resume where it left off once the bus is available again. to initiate a hold# condition, the device mu st be selected with cs# low. a hold# condition will activate on the falling edge of the hold# signal if the clk signal is already low. if the clk is not already low the hold# condition will activate after the next falling edge of clk. the hold# condition w ill terminate on the rising edge of the hold# signal if the clk signal is already low. if the clk is not already low the hold# condition will terminate after the next falling edge of clk. during a hold# condition, the serial data output (do) is high impeda nce, and serial data input (di) and serial clock (clk) are ignored. the chip select (cs#) signal should be kept active (low) for the full duration of the
ace25c 4 00 4 mb serial flash memory ver 1.2 7 hold# operation to avoid resetting the internal logic state of the device. figure 3 hold con dition waveform write protection applications that use non - volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern, the ACE25C400 provides severa l means to protect the data from inadvertent writes. write protect features ? device resets when vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and automatic write disable after erase or program ? softwa re and hardware (wp# pin) write protection using status register ? write protection using power - down instruction ? lock down write protection for status register until the next power - up ? one time program (otp) write protection for array and security secto rs using status register. upon power - up or at power - down, the ACE25C400 will maintain a reset condition while vcc is below the threshold value of vwi, (see 12.3 power - up timing and figure 23). while reset, all operations are disabled and no instruction s are recognized. during power - up and after the vcc voltage exceeds vwi, all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector erase, block erase, chip erase and the w rite status register instructions. note that the chip select pin (cs#) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay is reached. if needed a pull - up resister on cs# can be used to accomplish this. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, block erase, chip erase or write status register instr uction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write - disabled state of 0. software controlled write protection is facilitated using the write status register inst ruction and setting the status register protect (srp) and block protect (bp2, bp1 and bp0) bits. these settings allow a portion as small as a 4kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect (w p#) pin, changes to the status register can be enabled or disabled under hardware control. see status register section for further information. additionally, the power - down instruction offers an extra level of write protection as all instructions are ignor ed except for the release power - down instruction.
ace25c 4 00 4 mb serial flash memory ver 1.2 8 status register the read status register instruction can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, the state of write protection, security sector lock status. the write status register instruction can be used to configure the device write protection features and security sector otp lock. write access to the status register is controlled by the state of the non - volatile status regist er protect bit (srp), the write enable instruction, and the wp# pin. factory default for all status register bits are 0. figure 4 status register wip bit wip is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, sector erase, block erase, chip erase, write status register. during this time the device will ignore further instructions except for the read status register and erase/program suspend instruction (see t w , t pp , t se , t be , and t ce in 12.6 ac electrical characteristics). when the program, erase or write status register (or security sector) instruction has completed, the wip bit will be cleared to a 0 state indicating the device is ready for further instructions. write en able latch bit (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to 1 after executing a write enable instruction. the wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upo n power - up or after any of the following instructions: write disable, page program, sector erase, block erase, chip erase, write status register. block protect bits (bp2, bp1,bp0) the block protect bits (bp2, bp1, bp0) are non - volatile read/write bits in the status register (s4, s3, and s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in 12.6 ac electrical characteristics). all, none or a portion of the memory array ca n be protected from program and erase instructions (see table 2 status register memory protection). the factory default setting for the block protection bits is 0, none of the array protected.
ace25c 4 00 4 mb serial flash memory ver 1.2 9 status register protect bit / lock_bit (srp/lb) the status reg ister protect (srp) bit is operated in conjunction with the write protect (wp#) signal. the status register write protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (when the status register protect ( srp) bit is set to 1, and write protect (wp#) is driven low). in this mode, the non - volatile bits of the status register (srp, bp2, bp1, bp0) become read - only bits and the write status register (wrsr) instruction is no longer accepted for execution. in otp mode, this bit is served as lock_bit (lb), user can read/program/erase security sector as normal sector while lb value is equal 0, after lb is programmed with 1 by wrsr command, the security sector is protected from program and erase operation. the lb can only be programmed once. note : in otp mode, the wrsr command will ignore any input data and program lb to 1, user must clear the protect bits before enter otp mode and program the otp code, then execute wrsr command to lock the security sector before le aving otp mode. status register memory protection status register content memory content bp2 bit bp1 bit bp0 bit protect areas address density portion 0 0 0 none none none none 0 0 1 none none none none 0 1 0 none none none none 0 1 1 sector 0~ 119 00 0000h~0 77 fffh 480 kb lower 120/128 1 0 0 sector 0~ 111 000000h~0 6 ffffh 448 kb lower 112/128 1 0 1 sector 0~ 95 000000h~0 5 ffffh 384 kb lower 96/128 1 1 0 sector 0~ 63 000000h~0 3 ffffh 256 kb lower 64/128 1 1 1 all 000000h~0 7 ffffh 512 kb all instructions the st andard/dual spi instruction set of the ACE25C400 consists of 17 basic instructions that are fully controlled through the spi bus (see table 4~table 5 instruction set). instructions are initiated with the falling edge of chip select (cs#). the first byte of data clocked into the di input provides the instruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by addre ss bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge cs#. clock relative timing diagrams for each instruction are included in figure 5 through figure 27. all read instruct ions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (cs# driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignored. this feature further pro tects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has comp leted.
ace25c 4 00 4 mb serial flash memory ver 1.2 10 manufacturer and device identification op code mf7 - mf0 id15 - id0 id7 - do abh x x 11h 90h a1h x 11h 9fh a1h 3112h x standard spi instructions set (1) instruction name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0 - 7) (8 - 15) (16 - 23) (24 - 31) (32 - 39) (40 - 47) w rite enable 06h w rite disable 04h r ead status register 05h (s7 - s0) (2) write status register 01h (s7 - s0) (s15 - s8) page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 chip erase c7h/60h power - down b9h read data 03h a23 - a16 a15 - a8 a7 - a0 d7 - d0 fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy d7 - d0 release powerdown/id (4) abh dummy dummy dummy id7 - d0 (2) manufacturer/device id (4) 90h dum my dummy 00h (mf7 - mf0) (id7 - d0) jedec id (4) 9fh (mf7 - mf0) manufacturer (id15 - id8) memory type (id7 - d0) capacity enter otp mode 3ah dual spi instructions set instruction name byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 clock number (0 - 7) (8 - 15) (16 - 23) (24 - 31) (32 - 39) (40 - 47) fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0,) (6) fast read dual i/o bbh a23 - a8 (5) a7 - a0, m7 - m0 (5) (d7 - do,) (6) notes: 1. data bytes are shifted with most significant bit first. byte fields with d ata in parenthesis ( ) indicate data output from the device on 1 or 2 dq pins. 2. the status register contents and device id will repeat continuously until cs# terminates the instruction.
ace25c 4 00 4 mb serial flash memory ver 1.2 11 3. at least one byte of data input is required for page program and program security sectors, up to 512 bytes of data input. if more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. 4. see table 3 manufacturer and device identification t able for device id information. 5. dual spi address input format: dq 0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 dq 1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 6. dual spi data output format: dq 0 = (d6, d4, d2, d0) dq 1 = (d7, d5, d3, d1) write enable (wren) (06h) the write enable (wren) instruction (figure 5) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, sector erase, block eras e, chip erase, write status register instruction. the write enable (wren) instruction is entered by driving cs# low, shifting the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving cs# high. figure 5 write enable instruction write disable (wrdi) (04h) the write disable (wrdi) instruction (figure 6) resets the write enable latch (wel) bit in the status register to a 0. the write disable (wrdi) instruction is entered by driving cs# low, shi fting the instruction code 04h into the di pin and then driving cs# high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, page program, sector erase, block erase, chip erase instructions. figure 6 write disable instruction
ace25c 4 00 4 mb serial flash memory ver 1.2 12 read status register (rdsr) (05h) the read status register instructions allow the 8 - bit status registers to be read. the instruction is entered by driving cs# low and shifting the instruction code 05h into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 7. the status register bits are shown in figure 4 and include the wip, wel, bp2 - bp0 and srp bits. the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the wip status bit to be checked to determine when the cycle is complete and if the de vice can accept another instruction. the status register can be read continuously. the instruction is completed by driving cs# high. figure 7 read status register instruction write status register (wrsr) (01h) the write status register (wrsr) i nstruction allows the status register to be written. only non - volatile status register bits srp, bp2, bp1, bp0 can be written to. all other status register bit locations are read - only and will not be affected by the write status register (wrsr) instruction . the status register bits are shown in figure 4, and described in 10 status register. to write non - volatile status register bits, a standard write enable (06h) instruction must previously have been executed for the device to accept the write status regi ster (wrsr) instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving cs# low, sending the instruction code 01h, and then writing the status register data byte as illustrated in figure 8. to complete the write status register (wrsr) instruction, the cs# pin must be driven high after the eighth or sixteenth bit of data that is clocked in. if this is not done the write status register (wrsr) instruction will not be executed. during non - volatile statu s register write operation (06h combined with 01h), after cs# is driven high, the self - timed write status register cycle will commence for a time duration of t w (see 12.6 ac electrical characteristics). while the write status register cycle is in progres s, the read status register instruction may still be accessed to check the status of the wip bit. the wip bit is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to accept other instructions again. after the write sta tus register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0.
ace25c 4 00 4 mb serial flash memory ver 1.2 13 figure 8 writes status register instruction read data (03h) the read data instruction allows one or more data bytes to be sequential ly read from the memory. the instruction is initiated by driving the cs# pin low and then shifting the instruction code 03h followed by a 24 - bit address a23 - a0 into the di pin. the code and address bits are latched on the rising edge of the clk pin. afte r the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address after each byt e of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving cs# high. the read data instruction sequence is shown in figure 9. if a read data instruction is issued while an erase, program or write cycle is in process (wip =1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates fr om d.c. to a maximum of f r (see 12.6 ac electrical characteristics). the read data (03h) instruction is only supported in standard spi mode. figure 9 read data instruction
ace25c 4 00 4 mb serial flash memory ver 1.2 14 fast read (0bh) the fast read instruction is similar to the re ad data instruction except that it can operate at the highest possible frequency of fr (see 12.6 ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 10. the dummy clocks allow th e devices internal circuits additional time for setting up the initial address. during the dummy clocks the data value on the do pin is a dont care. figure 1 0 fast read instruction fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh) instruction except that data is output on two pins; dq0 and dq 1 . this allows data to be transferred from the ACE25C400 at twice the rate of standard spi devices. the fast read dual output instru ction is ideal for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of fr (see 12.6 ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 11. the dummy clocks allow the device's internal circuits additional time for setting up the initia l address. the input data during the dummy clocks is dont care. however, the dq 0 pin should be high - impedance prior to the falling edge of the first data out clock.
ace25c 4 00 4 mb serial flash memory ver 1.2 15 figure 11 fast read dual output instruction fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two i/o pins, dq 0 and dq 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits a23 - a0 two bits pe r clock. this reduced instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. fast read dual i/o with continuous read mode the fast read dual i/o instruction can further reduce instruction overhead thro ugh setting the continuous read mode bits (m7 - 0) after the input address bits a23 - a0, as shown in figure 12. the upper nibble of the (m7 - 4) controls the length of the next fast read dual i/o instruction through the inclusion or exclusion of the first byt e instruction code. the lower nibble bits of the (m3 - 0) are dont care (x). however, the dq pins should be high - impedance prior to the falling edge of the first data out clock. if the continuous read mode bits m5 - 4 = (1,0), then the next fast read du al i/o instruction (after cs# is raised and then lowered) does not require the bbh instruction code, as shown in figure 13. this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted lo w. if the continuous read mode bits m5 - 4 do not equal to (1,0), the next instruction (after cs# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. it is recommended to input ffffh on dq 0 for the next .
ace25c 4 00 4 mb serial flash memory ver 1.2 16 figure 1 2 fast read dual i/o instruction (initial instruction or previous m5 - 4 10) figure 1 3 fast read dual i/o instruction (previous instruction set m5 - 4=10)
ace25c 4 00 4 mb serial flash memory ver 1.2 17 page program (02h) the page program instruc tion allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel= 1). the i nstruction is initiated by driving the cs# pin low then shifting the instruction code 02h followed by a 24 - bit address a23 - a0 and at least one data byte, into the di pin. the cs# pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 14. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, a nd the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. one condi tion to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with th e write and erase instructions, the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after cs# is driven high, the self - timed page program instruction will commence for a time duration of t pp (see 12.6 ac electrical characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the wip bit. the wip bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page progra m instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits. figure 1 4 page program instruction
ace25c 4 00 4 mb serial flash memory ver 1.2 18 sector erase (20h) the sector erase instruction sets all memory within a specified s ector (4k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the cs# pin low and shifting the instruction code 20h followed a 24 - bit sector address a23 - a0 (see figure 1). the sector erase instruction sequence is shown in figure 15 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not do ne the sector erase instruction will not be executed. after cs# is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see 12.6 ac electrical characteristics). while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the wip bit. the wip bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see table 2 st atus register memory protection table). figure 1 5 sector erase instruction block erase (be) (d8h) the block erase instruction sets all memory within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction m ust be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the cs# pin low and shifting the instruction code d8h followed a 24 - bit block address a23 - a0. the bl ock erase instruction sequence is shown in figure 16. the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after cs# is driven high, the self - timed b lock erase instruction will commence for a time duration of t be (see 12.6 ac electrical characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the wip bit. the wi p bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see table 2 status register memory protection table).
ace25c 4 00 4 mb serial flash memory ver 1.2 19 figure 1 6 block erase instruction chip erase (ce) (c7 h / 60h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the inst ruction is initiated by driving the cs# pin low and shifting the instruction code c7h or 60h. the chip erase instruction sequence is shown in figure 17. the cs# pin must be driven high after the eighth bit has been latched. if this is not done the ch ip erase instruction will not be executed. after cs# is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see 12.6 ac electrical characteristics). while the chip erase cycle is in progress, the read status regis ter instruction may still be accessed to check the status of the wip bit. the wip bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the w rite enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, and bp0) bits. figure 1 7 chip erase instruction
ace25c 4 00 4 mb serial flash memory ver 1.2 20 power - down (b9h) a lthough the standby current during normal operation is relatively low, standby current can be further reduced with the power - down instruction. the lower power consumption makes the power - down instruction especially useful for battery powered applications ( see i cc1 and i cc2 in 12.6 ac electrical characteristics). the instruction is initiated by driving the cs# pin low and shifting the instruction code b9h as shown in figure 18. the cs# pin must be driven high after the eighth bit has been latched. if t his is not done the power - down instruction will not be executed. after cs# is driven high, the power - down state will enter within the time duration of t dp (see 12.6 ac electrical characteristics). while in the power - down state only the release from power - down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but o ne instruction makes the power down state a useful condition for securing maximum write protection. the device always powers - up in the normal operation with the standby current of i cc1 . figure 1 8 deep power - down instruction release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the device from the power - down state, or obtain the devices electronic identification (id) number. to release the device from the power - down state, the instruction is issued by driving the cs# pin low, shifting the instruction code abh and driving cs# high as shown in figure 19. release from power - down will take the time duration of tres1 (see 12.6 ac electrical characteristic s) before the device will resume normal operation and other instructions are accepted. the cs# pin must remain high during the tres1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the cs# pin low and shifting the instruction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 19. the device id value for the ace25c40 0 is listed in table 3 manufacturer and device identification table. the device id can be read continuously. the instruction is completed by driving cs# high.
ace25c 4 00 4 mb serial flash memory ver 1.2 21 when used to release the device from the power - down state and obtain the device id, the instr uction is the same as previously described, and shown in figure 20, except that after cs# is driven high it must remain high for a time duration of t res2 (see 12.6 ac electrical characteristics). after this time duration the device will resume normal ope ration and other instructions will be accepted. if the release from power - down / device id instruction is issued while an erase, program or write cycle is in process (when wip equals 1) the instruction is ignored and will not have any effects on the curren t cycle. figure 1 9 release power - down instruction figure 20 release power - down / device id instruction read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by driving the cs# pin low and shifting the instruction code 90h followed by a 24 - bit address a23 - a0 of 000000h. after which, the manufacturer id for ace technology co., ltd. (a1h) and the device id are shifted out on the falling edge of clk with most sign ificant bit (msb) first as shown in figure 21. the device id value for the ACE25C400 is listed in table 3 manufacturer and device identification table. if the 24 - bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id.
ace25c 4 00 4 mb serial flash memory ver 1.2 22 the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. figure 21 read manufacturer / device id instruction read jedec id (9fh) for compatibility reasons, the ACE25C400 provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories. the instruction is initiated by driving the cs# pin low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for ace technology co., ltd. (a1h) and two device id bytes, memory type (id15 - id8) and capacity id7 - d0 are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 22. for memory type and capacity values refer to table 3 manufacturer and device identification table.
ace25c 4 00 4 mb serial flash memory ver 1.2 23 figure 22 read jedec id instruction enter otp mode ( 3ah) this flash has an extra 256 bytes security sector, user must issue enter otp mode command to read, program or erase security sector. after entering otp mode, the security sector is mapping to sector 63, srp bit becomes lb and can be read with rdsr com mand. program / erase command will be disabled when lb is 1 wrsr command will ignore the input data and program lb to 1. user must clear the protect bits before enter otp mode. security sector can only be program and erase before lb equal 1 and bp[2:0] = 000. in otp mode, user can read other sectors, but program/erase other sectors only allowed when lb equal 0. user can use wrdi (04h) command to exit otp mode. sector sector size adress range 127 256 byte 07f000h - 07f0ffh table 6 security sector ad ress note: the secruty sector is mapping to sector 127
ace25c 4 00 4 mb serial flash memory ver 1.2 24 while in otp mode, user can use sector erase (20h) command only to erase otp data. figure 23 enter otp mode electrical characteristics absolute maximum ratings operating temperature - 40 to 85 cc +0.4v v cc - 0.5 to 4.0v n otice : stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only a nd functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabili ty. pin capacitance applicable over recommended operating range from: t a =25c, f=20 mhz, v cc =2.7v symbol test condition max units conditions c in (1) input capacitance 6 pf v in =0v c out (1) output c apa citance 8 pf v out =0v note: this parameter is characteri zed and is not 100% tested. power - up timing applicable over recommended operating range from: t a = - 40c to 85c, v cc =2.7v to 3.6v, (unless otherwise noted) parameter symbol spec unit min max vcc (min ) to cs# low t vsl 10 us time delay before write in struction t puw 1 10 ms
ace25c 4 00 4 mb serial flash memory ver 1.2 25 figure 24 power - up timing dc electrical characteristics applicable over recommended operating range from: t a = - 40c to 85c, v cc =2.7v to 3.6v, (unless otherwise noted). symbol parameter conditions spec unit mi n typ max v cc supply voltage 2.7 3.6 v i li input leakage current 2 ua i lo output leakage current 2 ua i cc1 standby current v cc =3.6v, cs#=v cc v in =v ss or v cc 1 5 ua i cc2 deep power - down current v cc =3.6v, cs#=v cc v in =v ss or v cc 1 5 ua i cc3 v cc =3.6v, clk=0.1, v cc /0.9vcc, at 100mhz, dq open 25 ma i cc4 operating current (wrsr) v cc =3.6v, cs#=v cc 8 12 ma i cc5 operating current (pp) v cc =3.6v, cs#=v cc 20 25 ma i cc6 operating current (se) v cc =3.6v, cs#=v cc 20 25 ma i cc7 operating current ( be) v cc =3.6v, cs#=v cc 20 25 ma v il (2) input low voltage - 0.5 0.3v cc v v ih (2) input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol =1.6ma v v oh output high voltage i oh = - 100ua v cc - 0.2 v v wi write inhibit threshold voltage 1.0 2.2 v
ace25c 4 00 4 mb serial flash memory ver 1.2 26 notes: 1. checker board pattern 2. v il min and v ih max are reference only and are not tested ac measurement conditions symbol parameter spec unit min max cl load capacitance 20 pf tr, tf input rise and fall times 5 ns vin input pulse voltage 0. 2 v cc to 0.8 v cc v in input timing reference voltages 0.3 v cc to 0.7 v cc v out o utput timing reference voltages 0.5 v cc v figure 25 ac measurement i/o waveform ac electrical characteristics applicable over recommended operating range from: t a = - 40c to 85c, v cc =2.7v to 3.6v, (unless otherwise noted). symbol parameter spec unit min typ max f r serial clock frequency for: fast_read, pp, se, be, dp, res, wren, wrdi, wrsr 100 mhz f r serial clock frequency for read, rdsr, rdid 66 mhz t ch (1) serial clock high time 4 ns t cl (1) serial clock low time 4 ns t clch (2) serial clock rise time (slew rate) 0.1 v/ns t chcl (2) serial clock fall time (slew rate) 0.1 v/ns t slch cs# active setup time 5 ns t chsh cs# active hold time 5 ns t shc h cs# not active setup time 5 ns t chsl cs# not active hold time 5 ns t shsl cs# high time (for array read ? array read) 100 ns t shqz (2) output disable time 6 ns t clqx output hold time 0 ns t dvch data in setup time 2 ns t chdx data in hold t ime 5 ns
ace25c 4 00 4 mb serial flash memory ver 1.2 27 t hlch hold# low setup time ( relative to clk ) 5 ns t hhch hold# high setup time ( relative to clk ) 5 ns t chhh hold# low hold time ( relative to clk ) 5 ns t chhl hold# high hold time ( relative to clk ) 5 ns t hlqz (2) hold# low to hi gh - z output 6 ns t hhqx (2) hold# high to low - z output 6 ns t clqv output valid from clk 8 ns t whsl write protect setup time before cs# low 20 ns t shwl write protect hold time after cs# high 100 ns t dp (2) cs# high to deep power - down mode 3 us t res1 (2) cs# high to standby mode without electronic signature read 3 us t res2 (2) cs# high to standby mode with electronic signature read 1.8 us t w write status register cycle time 10 15 ms t pp page programming time 1.5 5 ms t se sector erase ti me 0.09 0.3 s t be block erase time (64kb) 0.5 2 s t ce chip erase time 3.5 10 s notes: 1. t clkh +t clkl >= 1 / f clk 2. this parameter is characterized and is not 100% tested. figure 26 serial output timing figure 27 serial input timin g
ace25c 4 00 4 mb serial flash memory ver 1.2 28 figure 28 hold timing
ace25c 4 00 4 mb serial flash memory ver 1.2 29 packaging information sop - 8
ace25c 4 00 4 mb serial flash memory ver 1.2 3 0 packaging information tdfn - 8
ace25c 4 00 4 mb serial flash memory ver 1.2 31 notes ace does not assume any responsibility for use as critical components in life support devices or systems without the express written approva l of the president and general counsel of ace electronics co., ltd. as sued herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and shoes failure to perf orm when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ace technology co., ltd. h ttp://www.ace - ele.com/

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